The present invention relates to arranging a signal line in an integrated circuit (IC) to yield a desired capacitance.
An IC may use long transmission lines (e.g., greater than ten microns) to transmit clock signals to different areas in the chip. When doing so, the transmission line may cross into different voltage domains in the IC which may introduce distortion into the clock signal—e.g., duty cycle distortion or jitter. Moreover, because of the length of the transmission line, the IC may need to divide the transmission line into smaller segments where each segment has a buffer for removing distortion and transmitting the clock signal along the next segment. For example, for a 100 micron transmission line, the IC may have five buffers spaced evenly along the transmission line to retransmit the clock signal to the next buffer.